eFPGA is available now on mainstream process nodes (40, 28 and 16), in sizes from 200 LUTs to 200K LUTs and with options for DSP and RAM integration to fit almost any customer need.
Flex Logix has been working for some time with multiple customers on integrating eFPGA with their CPUs: ARM, RISC-V, Tensilica and others. Bus interfaces include AXI, AHB, APB and TL. Our lead customer has working silicon of their CPU with eFPGA. More are in design/evaluation.
The most common application is to use eFPGA as a reconfigurable accelerator which can accelerate performance for common, heavy workloads 30-100x faster than the CPU: see our app note that describes the details of 4 common accelerators (AES, SHA, FFT and JPEG Encoder) benchmarked against an ARM processor on this web page: http://www.flex-logix.com/accelerators/
Other applications include reconfigurable serial I/O and reconfigurable processor instructions.
Below we’ll discuss details of integrating ARM and RISC-V processors with eFPGA.
Integrate ARM with eFPGA NOW
As well, we have designed a complete “reference design”: the FlexMicro, which is implemented in RTL on our soon-to-be-available EFLX200K evaluation board:
The FlexMicro design uses a Cortex-M0 with Silvaco peripherals and bus IP to implement a complete microcontroller with AHB and APB bus interfaces to an EFLX array which can configure and reconfigure whatever accelerators the customer wants to test out, including with direct GPIO connections. This is an “architectural breadboard” for architects to experiment with eFPGA architectures for CPU acceleration before fixing on a design for their silicon.
Integrate RISC-V with eFPGA NOW
For a very low price, any customer can have SiFive build them ~100 prototypes of a custom U500 that meets their needs: 1-8 U5 RISC-V cores, custom coprocessor (if desired), custom accelerator on the processor bus, and even custom I/O.
eFPGA is a custom accelerator option that is available for SiFive Platform chips. For 28nm, there is expected to be 2 or 3 eFPGA size options with integrated RAM (since most customer RTL requires scratchpad RAM) connected to the full-speed TL bus (the TL bus is SiFive’s version of AXI). An app note will be available shortly detailing TL bus interfaces with Verilog RTL files.
One of the expected eFPGA configurations in 28nm is shown below: 16K LUTs with ~1Mbit of embedded RAM integrated within the array. Embedded RAM is integrated because many of the accelerator functions require them – the ratio of bits to LUTs is similar to a Xilinx FPGA. The RAMs are integrated within the array so that all of the external I/O are available for integration in the SoC. The cores can optionally be all LUTs or can be the DSP version, which swaps out about 20% of the LUTs for 40 MACs. The EFLX eFPGA will directly connect to the TL (tilelink) processor bus (the RISC-V equivalent to AXI) and can connect directly to up to 64 GPIO.
We will deliver the GDS to SiFive in early 2018 for their 28nm Platform reference design/boards. Later in 2018, you will be able to order from SiFive your custom 28nm SoCs with the eFPGA/RAM you need for your application.
SiFive’s 180nm MCU Platform is already available in silicon. We have committed to support it with 180nm eFPGA “on demand” – we’ll port to the 180nm process when the first customer requests it from SiFive, and expect it will take ~6 months to deliver.
eFPGA + CPU is Available NOW
SiFive will deliver their Platform reference design in 28nm with eFPGA in 2018 and will be taking orders for customized 28nm SoCs with multiple eFPGA options in 2018.
eFPGA + CPU is a reality.